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| INTEGRATED CIRCUITS 74ALS109A Dual J-K positive edge-triggered flip-flop with set and reset Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset 74ALS109A DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. The J and K inputs must be stable just one setup time prior to the Low-to-High transition of the clock for predictable operation. The JK design allows operation as a D flip-flop by tying J and K inputs together. Although the clock input is level sensitive, the positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation. TYPICAL SUPPLY CURRENT (TOTAL) 3.0mA PIN CONFIGURATION RD0 J0 K0 CP0 SD0 Q0 Q0 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RD1 J1 K1 CP1 SD1 Q1 Q1 SF00135 TYPE 74ALS109A TYPICAL fMAX 150MHz ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C 74ALS109AN 74ALS109AD DRAWING NUMBER SOT38-4 SOT109-1 16-pin plastic DIP 16-pin plastic SO INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS J0, J1 K0, K1 CP0, CP1 SD0, SD1 RD0, RD1 Q0, Q1, Q0, Q1 J inputs K inputs Clock inputs (active rising edge) Set inputs (active-Low) Reset inputs (active-Low) Data outputs DESCRIPTION 74ALS (U.L.) HIGH/LOW 1.0/2.0 1.0/2.0 1.0/2.0 1.0/4.0 1.0/4.0 20/80 LOAD VALUE HIGH/LOW 20A/0.2mA 20A/0.2mA 20A/0.2mA 20A/0.4mA 20A/0.4mA 0.4mA/8mA NOTE: One (1.0) ALS unit load is defined as: 20A in the High state and 0.1mA in the Low state. LOGIC SYMBOL 2 14 3 13 IEC/IEEE SYMBOL 2 4 6 1J C1 1K R S 4 5 1 12 11 15 CP0 SD0 RD0 CP1 SD1 RD1 J0 J1 K0 K1 3 1 5 7 14 Q0 Q0 Q1 Q1 12 13 15 6 7 10 9 11 2J C2 2K R S 10 9 VCC = Pin 16 GND = Pin 8 SF00136 SF00137 1991 Feb 08 2 853-1275 01670 Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset 74ALS109A LOGIC DIAGRAM 5, 11 FUNCTION TABLE INPUTS OUTPUTS J X X X h l h l l K X X X l l h h h Q H L H* q L H q q Q L H H* q H L q q SD L RD H L L H H H H H CP X X X L OPERATING MODE Asynchronous set Asynchronous reset Undetermined* Toggle Load "0" Load "1" Hold "no change" Hold "no change" SD RD CP 1, 15 4, 12 6, 10 Q H L H 7, 9 Q H H J 2, 14 H 3, 13 H K VCC = Pin 16 GND = Pin 8 SC00042 H = High voltage level h = High state must be present one setup time prior to Low-to-High clock transition L = Low voltage level l = Low state must be present one setup time prior to Low-to-High clock transition q = Lower case indicate the state of the referenced output prior to the Low-to-High clock transition X = Don't care = Low-to-High clock transition * = The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the set and reset are near VIN maximum. Furthermore, this configuration is nonstable; that is, it will not remain when either set or reset returns to its inactive (High) level. ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in high output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 16 0 to +70 -65 to +150 UNIT V V mA V mA C C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VIH VIL IIk IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 -18 -0.4 8 +70 NOM 5.0 MAX 5.5 V V V mA mA mA C UNIT 1991 Feb 08 3 Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset 74ALS109A DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH VO OL VIK II PARAMETER High-level output voltage Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High level input current High-level Jn, Kn, CPn SDn, RDn Jn, Kn, CPn IIH SDn, RDn Jn, Kn, CPn IIL IO ICC Low-level Low level input current Output current3 (total)4 SDn, RDn VCC = MAX, VI = 0 4V MAX 0.4V VCC = MAX, VO = 2.25V VCC = MAX -30 3.0 VCC = MAX, VI = 2 7V MAX 2.7V VCC = MAX, VI = 7 0V MAX 7.0V TEST CONDITIONS1 VCC = 10%, VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX, , , VIH = MIN VCC = MIN, II = IIK IOH = -0.4mA IOL = 4mA IOL = 8mA LIMITS MIN VCC - 2 0.25 0.35 -0.73 0.40 0.50 -1.5 0.1 0.2 20 40 -0.2 -0.4 -112 4.0 TYP2 MAX UNIT V V V V mA mA A A mA mA mA mA Supply current NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs High in turn. AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL Maximum clock frequency Propagation delay CPn to Qn or Qn Propagation delay SDn or RD to Qn or Qn Waveform 1 Waveform 1 Waveform 2, 3 80 3.0 3.0 1.0 3.0 14.0 14.0 8.0 10.0 MAX MHz ns ns UNIT AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN tsu (H) tsu (L) th (H) th (L) tw (H) tw (L) tw (L) trec Setup time, High or Low Jn, Kn to CPn Hold time, High or Low Jn, Kn to CPn CPn Pulse width High or Low SDn or RDn Pulse width Low Recovery time, SDn or RDn to CPn Waveform 1 Waveform 1 Waveform 1 Waveform 2, 3 Waveform 2, 3 6.0 6.0 0.0 0.0 6.0 6.0 6.0 6.0 MAX ns ns ns ns ns UNIT 1991 Feb 08 4 Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset 74ALS109A AC WAVEFORMS For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance. Jn, Kn VM tsu(L) VM th(L) 1/fmax VM tsu(H) VM th(H) CPn VM tw(H) tPLH VM tw(L) VM tPHL Qn VM tPHL VM tPLH Qn VM VM SC00043 Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, Clock Width, and Maximum Clock Frequency Jn, Kn Jn, Kn SDn VM tw(L) VM tREC RDn VM tw(L) VM tREC CPn VM CPn VM tPLH Qn tPHL Qn VM Qn VM Qn tPLH VM tPHL VM SC00044 SC00045 Waveform 2. Propagation Delay for Set to Output, Set Pulse Width and Recovery Time for Set to Clock Waveform 3. Propagation Delay for Reset to Output, Reset Pulse Width and Recovery Time for Reset to Clock 1991 Feb 08 5 Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset 74ALS109A TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tff) CL RL tw VM 10% tTLH (tr ) 0.3V 90% AMP (V) tTLH (tr ) 90% tTHL (tf ) AMP (V) 90% VM tw 10% 0.3V Test Circuit for Totem-pole Outputs POSITIVE PULSE 10% VM DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. Input Pulse Definition INPUT PULSE REQUIREMENTS Family Amplitude VM 74ALS 3.5V 1.3V Rep.Rate 1MHz tw 500ns tTLH 2.0ns tTHL 2.0ns SC00005 1991 Feb 08 6 Philips Semiconductors Product specification Dual J-K positive edge-triggered flip-flop with set and reset 74ALS109A DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 1991 Feb 08 7 Philips Semiconductors Product specification Dual J-K positive edge-triggered flip-flop with set and reset 74ALS109A SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 1991 Feb 08 8 Philips Semiconductors Product specification Dual J-K positive edge-triggered flip-flop with set and reset 74ALS109A DEFINITIONS Data Sheet Identification Objective Specification Product Status Formative or in Design Definition This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Preliminary Specification Preproduction Product Product Specification Full Production Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 1991 Feb 08 9 |
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